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| !""# $!%!! &'( !""# %!) *+ ,- - . description signal address input a0~a18 data input/output d0~d7 chip select /cs write enable /we output enable /oe no connect nc power v cc ground gnd 512k x 8 sram /cs /oe /we d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a9 a10 a11 a12 a13 a14 a15 a16 a8 a17 a18 ! "#$ %& ' ( ) *+,-) )-).), /0 ) , 1- 0%#02 ,)/ 3 45 4) 6 ) . 7 ,/8 6 0 7 8 6 ) $8)9-/) 5 -,! ) 4 ) : !, ) ; ! " # $ 9 &" $ %%& " $< = ,: : / ) ,))8 ;. 4 ! ", $ 9,: : / ) , ,-) )-).), 9 ) : ,-) ., 8 )8 ;. . - 9 - " ( ! / ),) ! : 65 6>,965++ ;. pinout (top view) a4 1234 56 a b c d e f g h /cs a2 a0 a17 a15 nc nc d0 v cc v ss d3 nc nc a1 a16 nc nc nc a18 a9 nc nc a12 a10 a8 a6 d4 v cc v ss d7 a3 /oe nc d1 nc d6 d5 a14 d2 nc nc a5 a13 /we nc a7 a11 note : pinout shows top view, balls facing down. pin a1 ident. parameter symbol min typ max unit supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 - vcc+0.3 v input low voltage v il -0.3 - 0.8 v operating temperature t a 0 - 70 o c t ai -40 - 85 o c (i suffix) %& '( ( ))* ) + , parameter symbol min max unit voltage on any pin relative to v ss v t -0.5 to 4.6 v power dissipation p t 1 w storage temperature t stg -55 to +150 o c parameter symbol test condition min typ max unit input leakage current i li v in =v ss to v cc -2 - 2 a output leakage current i lo /cs=v ih or /oe=v ih or /we=v il , v out =v ss to v cc -2 - 2 a operating supply current i cc1 min. cycle, 100% duty /cs=v il , v in =v ih or v il , i out =0ma - - 170 ma standby supply current i sb min. cycle, /cs=v ih - - 60 ma i sb1 f=0mhz, cs> v cc -0.2v, v in > v cc -0.2v or v in < 0.2v - - 15 ma output voltage v ol i ol =8.0ma - - 0.4 v v oh i oh =-4.0ma 2.4 - - v 166? 30pf i/o pin 1.76v parameter symbol test condition typ max unit input capacitance c in v in =0v - 10 pf i/o capacitance c i/o v i/o =0v - 10 pf - ) *. ) + - -:? & % & + -) ,! ?% + -,6- - .)!):? "& 6- -3 ,?3 , .) & @%%& ' ( /cs /we /oe mode i/o pin supply current h x x not select high-z i sb ,i sb1 l h h output disable high-z i cc l h l read d out i cc l l x write d in i cc !"#$ () $ / $ 15 20 parameter symbol min max units write cycle time t wc 15 - 20 - ns chip select to end of write t cw 12 - 14 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 12 - 14 - ns write pulse width (/oe high) t wp 12 - 14 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 7 0 9 ns data to write time overlap t dw 7 - 9 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 3 - 3 - ns 15 20 parameter symbol min max min max units read cycle time t rc 15 20 - ns address access time t aa - 15 - 20 ns chip select to output t co - 15 - 20 ns output enable to valid output t oe - 7 - 9 ns chip enable to low-z output t lz 3 - 3 - ns output enable to low-z output t olz 0 - 0 - ns chip disable to high-z output t hz 0 7 0 9 ns output disable to high-z output t ohz 0 7 0 9 ns output hold from address change t oh 3 - 3 - ns () $ ,,) ) , #@#61@& #71@& () $ #71@& previous data valid data valid address data out t rc t aa t oh address data out valid data t rc t aa t co t olz t lz(4,5) t hz(3,4,5) t ohz t oh /cs /oe notes (read cycle) 1. /we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with /cs=v il . 7. address valid prior to coincident with /cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. t oe / $ #61@ ; valid data address /oe /cs data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t dw t dh t ohz(6) high z high z(8) /we notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. / $ #61@3 4a , /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) high z high z(8) /we valid data t dw t dh t ow (10) (9) notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. / $ 0 #@ ) , /cs address data in data out t wc t aw t wr(5) t cw(3) t as(4) t wp(2) t whz(6) high z high z(8) /we valid data t dw t dh t lz high z high z notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /cs and /we. a write begins at the latest transition /cs going low and /we going low ; a write ends at the earliest transition /cs going high or /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /cs or /we going high. 6. if /oe, /cs and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if /cs goes low simultaneously with /we going or after /we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when /cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. ! " ,1 2% 3) general reliability data high temperature operating life 125 o c / 6v / 1000hrs high temperature storage life 150 o c / 1000hrs autoclave 121 o c / 100% rh / 168hrs temperature cycling -55 ~ 125 o c / 1000 cycles moisture sensitivity jedec level 3 30 o c / 60% rh / 192hrs o ja thermal performance 30 ~ 45 o c/watt 10.00 max. 8.00 max . 1.40 max. top view pin a1 ident. 1.00 +0.07 c l 1.00 +0.07 c l a1 h6 bottom view # *)" ! " ! ##$ %&$' %#% % $ % % %% % %#$ % ( $$ % &'$# % ! $& %&$ ) $ # $)$) *$)$ # $!+# #% %)$#& " )'%, ' !# % ( % # $ # $ % $ &$ #$ # #')%% % & ))$ " # ( -)$ ($ % ))$" & #') % $#$ ! "# $ $% #& "#% # ! #& ! "'() *# " +", * - # ./ # 0 1 2 20% . 3 . - -## # # . )- |
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